Field
The embodiments herein generally relate to an etching process for etching a dielectric layer with high selectivity.
Description of the Background Art
Reliably producing submicron and smaller features is one of the key requirements of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, with the continued miniaturization of circuit technology, the dimensions of the size and pitch of circuit features, such as interconnects, have placed additional demands on processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise imaging and placement of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is critical to further increases in device and interconnect density. Additionally, forming sub-micron size features and interconnects with reduced waste of intermediate materials, such as resists and hardmask materials, is desired.
As feature sizes have become smaller, the demand for higher aspect ratios, defined as the ratio between the depth of the feature and the width of the feature, has steadily increased to 20:1 and even greater. Developing etch processes that are capable of reliably forming features with such high aspect ratios presents a significant challenge. Traditionally, features in a material layer having aspect ratios of about 10:1 or so were fabricated by anisotropically etching dielectric layers to a predetermined depth and width.
During etching, redeposition or build-up of by-products or other materials generated during the etching process may accumulate on the top and/or sidewalls of the features being etched, thereby blocking the opening of the feature being formed in the material layer. As the opening of the etched features are narrowed and/or sealed by the accumulated redeposition material, the reactive etchants are prevented from reaching the lower surface of the features, thereby limiting the aspect ratio that may be obtained. Additionally, as the redeposition material or build-up of by-products may be randomly and/or irregularly adhere to the top surface and/or sidewalls of the features being etched, the resulting irregular profile and growth of the redeposition material may alter the flow path of the reactive etchants, thereby resulting in a bowing or twisting profile of the features formed in the material layer.
Furthermore, in some cases, after the etching process, the corners features often suffer from rounded top shoulder erosion or undesired non-vertical sidewall etched profile, resulting in critical dimension (CD) loss or deformed profiles. In accurate profile or structural dimensions may result in collapse of the device structure, eventually leading to device failure and product low yield. Poor etching selectivity and control occurring during manufacturing processes for such shapes or features in the material layer may undesirably result in an inaccurate profile control, thereby eventually leading to device failure.
Therefore, there is a need in the art for improved methods for etching features with high aspect ratios.